----------------------------------------------------------------------
-- Bit-serial 16-bit subtraction unit
-- Stephen West, James Carroll
-- BYU ECEn 620, October 2008
----------------------------------------------------------------------
Library ieee;
	use ieee.std_logic_1164.all;
	use ieee.numeric_std.all;
	-- latency 0 clk
entity BitSerialSub16 is
	generic(
		word_length:integer:=8;
		code_vector_length:integer:=16;
		system_word_length:integer:=12
	);
	port(
		clk, lsb_in : in std_logic;
		a_in, b_in : in std_logic_vector(code_vector_length-1 downto 0);
		sub_out : out std_logic_vector(code_vector_length-1 downto 0);
		lsb_out: out std_logic
	);
end entity;

architecture BitSerialSub16 of BitSerialSub16 is
	component BitSerialSub is
		generic(
			word_length:integer:=8;
			code_vector_length:integer:=16;
			system_word_length:integer:=12
		);
		port(
			clk, a_in, b_in, lsb_in:in std_logic;
				sub_out, lsb_out: out std_logic
		);
	end component;
	signal lsb_out_vector: std_logic_vector(code_vector_length-1 downto 0);
begin
	sub16x:for N in 0 to code_vector_length-1 generate
		sub:BitSerialSub port map(clk=>clk, a_in=>a_in(N), b_in=>b_in(N), lsb_in=>lsb_in,
								sub_out=>sub_out(N), lsb_out=>lsb_out_vector(N));
	end generate;
	lsb_out<=lsb_out_vector(0);
end architecture;
